NXP Semiconductors /LPC43xx /ETHERNET /MAC_TIMESTP_CTRL

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Interpret as MAC_TIMESTP_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TSENA)TSENA 0 (TSCFUPDT)TSCFUPDT 0 (TSINIT)TSINIT 0 (TSUPDT)TSUPDT 0 (TSTRIG)TSTRIG 0 (TSADDREG)TSADDREG 0RESERVED 0 (TSENALL)TSENALL 0 (TSCTRLSSR)TSCTRLSSR 0 (TSVER2ENA)TSVER2ENA 0 (TSIPENA)TSIPENA 0 (TSIPV6ENA)TSIPV6ENA 0 (TSIPV4ENA)TSIPV4ENA 0 (TSEVNTENA)TSEVNTENA 0 (TSMSTRENA)TSMSTRENA 0TSCLKTYPE 0 (TSENMACADDR)TSENMACADDR

Description

Time stamp control register

Fields

TSENA

Time stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode.

TSCFUPDT

Time stamp Fine or Coarse Update When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled.

TSINIT

Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete.

TSUPDT

Time stamp Update This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware.

TSTRIG

Time stamp Interrupt Trigger Enable This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt.

TSADDREG

Addend Reg Update When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected.

RESERVED

Reserved

TSENALL

Enable Time stamp for All Frames When set, the Time stamp snapshot is enabled for all frames received by the core.

TSCTRLSSR

Time stamp Digital or Binary rollover control When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value.

TSVER2ENA

Enable PTP packet snooping for version 2 format When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format.

TSIPENA

Enable Time stamp Snapshot for PTP over Ethernet frames When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets.

TSIPV6ENA

Enable Time stamp Snapshot for IPv6 frames When set, the Time stamp snapshot is taken for IPv6 frames.

TSIPV4ENA

Enable Time stamp Snapshot for IPv4 frames When set, the Time stamp snapshot is taken for IPv4 frames.

TSEVNTENA

Enable Time stamp Snapshot for Event Messages When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling.

TSMSTRENA

Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node.

TSCLKTYPE

Select the type of clock node The following are the options to select the type of clock node: 00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock

TSENMACADDR

Enable MAC address for PTP frame filtering When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet.

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